The present invention relates generally to vertical transistor structures in the trench capacitors of Dynamic Random Access Memory (DRAM) cells and, more specifically, to a process for manufacture of such structures.
Semiconductor memory devices comprising vertical transistor structures in trench capacitors are well known in the art to save surface area on electronic circuits such as DRAM chips. FIG. 1 schematically illustrates a typical semiconductor memory device. A more detailed depiction of such a semiconductor memory device is provided in FIG. 12. Semiconductor memory device 10 comprises a capacitor trench 12, an isolation or xe2x80x9ctrench topxe2x80x9d oxide (TTO) 14, a gate oxide 16, diffusion regions (contact implants) 18, a gate contact 220, a source contact 222, and gate sidewall isolation spacers 240. Of the elements of semiconductor memory device 10, only gate contact 220, source contact 222, and gate sidewall isolation spacers 240 are above the surface 21 of the substrate 24, which is typically a silicon wafer.
FIG. 2 is a cross section taken along line 2xe2x80x942 in FIG. 1. As shown in FIG. 2, gate oxide 16 forms a continuous faceted wall formed of planes aligned with the (100) and (110) crystal planes for a silicon wafer with a (100) surface orientation. The silicon wafer may have any surface orientation, however, as is known in the art.
A crystal contains planes of atoms which influence the properties and behavior of a material. Thus, it is advantageous to identify various planes within crystals. In accordance with standard crystallographic nomenclature, such identification is done using Miller indices: three numbers within parentheses, namely (hkl). A plane that intersects the x, y, and z axes at 1, 1, and 0.5, respectively, is represented as (112). The Miller indices are the reciprocals of the three axial intercepts for a plane, cleared of fractions and common multipliers.
Further in accordance with standard crystallographic nomenclature, various symbols have specified meanings. Among those symbols are rounded brackets, { }, which refer to families of equivalent crystallographic planes (e.g., the {001} family of planes); parentheses, ( ), which refer to specific crystallographic planes (e.g., the (100) plane); horizontal triangles, ⋄, which refer to families of equivalent crystallographic axes (e.g., the  less than 011 greater than  family of axes); and square brackets, [ ], which refer to a specific crystal axis (e.g., the [110] axis). For example, in silicon crystals, the (100) plane and the (001) plane are equivalent to one another and, thus, are both in the same {001} family of planes.
The oxidation step used to form gate oxide 16 is strongly crystal orientation dependent. That is, the thickness of the oxide formed after a given time at a given temperature is dependent on the crystal orientation of the underlying silicon. Thus, the gate oxidation step tends to form gate oxide 16 with a thickness d1 in the (110) planes that is greater than thickness d2 in the (100) planes. The non-homogenous gate oxide thickness leads to weak points at the thinner sections where the time to breakdown is reduced relative to the rest of the gate oxide.
Similarly, the crystal dependency during oxidation steps also affects the creation of other oxides in DRAM trench structures, such as the xe2x80x9cLOCOS collar,xe2x80x9d described below. Referring now to FIGS. 3-12, in which like reference numbers refer to like elements throughout, there is shown various aspects of an exemplary DRAM cell and intermediate steps in an exemplary process for making the cell. These process steps are disclosed by U.S. patent application Ser. No. 09/359,292 filed on behalf of Gary Bronner et al., assigned to the common assignee of this invention, and incorporated herein by reference.
As shown in FIG. 3, a typical deep trench storage capacitor of semiconductor memory device 10 is formed into a pad 22 and a substrate 24 by conventional processing techniques well known in the art. For example, an optical lithography step may be used to form a pattern on pad 22. Then a dry etching step, such reactive-ion etching (RIE), may be used to create a trench 20 to a desired depth through pad 22 and into substrate 24.
Deep trench 20 generally has a depth of about 3 xcexcm to about 10 xcexcm and a diameter or maximum width that is a function of the lithographic ground rule, typically about 0.5 xcexcm to less than 0.1 xcexcm. Trench 20 has sidewalls 32 and a bottom 33.
As shown in FIG. 4, an isolation collar 26 is formed in an upper region 28 of trench 20. Upper region 28 typically comprises 10-20% of the total depth of trench 20. Collar 26 may be formed using a local thermal oxidation (LOCOS) process, such as by the exemplary process explained below, or by other physical and chemical mechanisms, as also indicated below. Because of the traditional use of the LOCOS process, isolation collar 26 is sometimes referred to as a LOCOS collar.
Before the oxidation step, a barrier film (not shown) may be formed along the exposed surfaces of trench 20 and pad 22 such as by a low-pressure chemical vapor deposition (LPCVD) of a SiN film having a thickness of about 2 nm to about 10 nm. The barrier film is then removed from upper region 28, for example by filling trench 20 with photoresist (not shown) and partially etching the photoresist down into trench 20 to a depth controlled by the amount of overetch time. This step exposes the barrier film in upper region 28 while leaving the lower region 30 covered. The exposed barrier film may then be removed in upper region 28 of trench 20 and from pad layer 22, for example, by chemical or dry etching, and then the photoresist stripped away. Other processes for isolating sidewall 32 in upper region 28 while protecting sidewall 32 in lower region 30 may also be used.
The local oxidation step is then performed. The oxidation step may be conducted, for example, at oxidation conditions that promote the oxidation rate along one family of crystal axes over another. Such oxidation conditions induce faceting of the underlying silicon substrate 24 during growth of collar 26. Such a faceted collar may have a cross section similar to that shown for gate oxide 16 as illustrated in FIG. 2, where thickness di of the oxide aligned with one plane is greater than thickness d2 of the oxide aligned with another crystal plane. Because of the different oxidation rates of the different crystal orientations, in order to achieve a minimum collar thickness on all of the sidewalls, regardless of crystal orientation, an unnecessary, increased thickness may be required on the sidewall having the faster-growing orientation. The thermal oxide collar 26 and associated faceting are formed only on sidewalls 32 in upper region 28 of trench 20; the barrier film protects sidewalls 32 in lower region 30 of trench 20.
Next, the barrier film in lower region 30 is typically stripped via a process that selectively leaves thermal oxide isolation collar 26 in upper region 28 of trench 20. A buried plate 34 is then created in lower region 30, leaving the configuration shown in FIG. 4. Buried plate 34 may be created by doping lower region 30 of trench 20 to form an out-diffusion in substrate 24 using collar 26 as a mask for upper region 28. The out-diffusion may be formed using arsenosilicate glass (ASG) drive-in, plasma doping (PLAD), plasma ion implantation (PIII), gas-phase diffusion of arsenic (As) or phosphorus (P), or other techniques known in the art.
Next, as shown in FIG. 5, a thin node dielectric 35 is created, such as by thermal nitridation, for example with ammonia (NH3), followed by LPCVD of SiN. Finally, trench 20 is filled, such as with an n+ doped LPCVD polysilicon 36, and recessed to a desired depth D1. Depth D1 is typically about 300 nm to about 700 nm, preferably between 300 to 450 nm.
Isolation collar 26 is then etched away, such as with a wet etch using a solution containing hydrogen fluoride (HF), to expose sidewalls 32 in the area where the collar 26 is not covered by polysilicon 36 and below the polysilicon level to a depth D2, as shown in FIG. 6. D2 is typically about 10 nm to about 50 nm.
Next, as shown in FIG. 7, a buried strap 40 is formed. Typically of LPCVD silicon, buried strap 40 is formed in a layer having a thickness of about 10 nm to about 50 nm. As shown in FIG. 8, buried strap 40 is then removed from sidewalls 32 of trench 20 above polysilicon 36 and above pad 22, such as by an isotropic wet chemical or dry etching step.
Then, as shown in FIG. 9, trench-top dielectric 14 or trench-top oxide (TTO) is formed, such as by an anisotropic high-density plasma (HDP) or other bias-assisted oxide deposition step. The creation of trench-top dielectric 14 typically forms a corresponding layer (not shown) atop pad 22, which is removed by a chemical mechanical polishing (CMP) step as is known in the art. Thus exposed, pad 22 is then stripped, typically by a wet chemical etch step selective to trench-top dielectric 14, and a sacrificial oxide 44 is grown on the exposed surface of substrate 24 and exposed sidewall 32 of trench 20, as shown in FIG. 9.
Ion implantation may then be used to create a p-well 50 and an n-band 52 below p-well 50 in substrate 24. Similarly, ion implantation of As or P may be used to create diffusion region 18. Another diffusion region 62 is created by out-diffusion from n+ doped polysilicon region 36 through buried strap 40. Such process steps yield the structure shown in FIG. 9. Other device-threshold-tailoring implants may also be created at this time.
Next, as shown in FIG. 10, sacrificial oxide 44 is removed, such as by a chemical wet etch process with an HF-containing solution. Then, gate oxide 16 is grown and a conductive gate layer 48, such as polysilicon having a thickness approximately equal to the diameter of trench 20, is formed. A nitride pad (not shown) is formed having a thickness of approximately half to approximately equal to the thickness of gate layer 48.
An active area 54 is patterned (see FIG. 11), typically by photolithography, and an etching step, such as RIE, is performed to etch shallow trench isolation (STI) regions 46 everywhere except in active area 54. STI regions 46 are filled, typically with an oxide, and planarized by a CMP step down to the pad nitride. The pad nitride is then stripped away, leaving the structure shown in FIG. 10.
Next, a thin seed layer of polysilicon is typically deposited, extending polysilicon gate layer 48 over the edge of trench 20 and over top diffusion region 62 in p-well 50 of substrate 24. A middle layer 56, which typically comprises a higher conductivity material than polysilicon gate layer 48, such as tungsten (W) or tungsten silicide (WS), is then formed. Finally, a gate cap layer 58, comprising SiN or silicon oxide, is formed. The gate conductor layers are then patterned by lithography and dry etched, leaving the gate contact 220 (comprising gate layer 48, middle layer 56, and gate cap 58) shown in FIG. 12.
Next, sidewall isolation spacers 240, typically comprising silicon nitride, silicon oxide, or a combination of those materials, are created by processes well-known in the art to electrically isolate the wordline (gate contact 220) from the bitline (the source or diffusion contact 222). Spacers 240 are typically created by depositing a conformal coating of SiN of about 10 nm to about 100 nm, and performing an anisotropic dry spacer etch process to leave the spacers 240 only on the sidewalls of gate contact 220. At this time, optional added implants may be performed to tailor source and drain regions (diffusion regions 18 and 62) of the transistor.
Next, the isolating regions between multiple gate contacts 220 on the wafer are typically filled with an interlevel dielectric 63, and contact holes are etched via lithography and dry etching to create the holes in which to form source contact 222. Source contact 222 typically comprises doped polysilicon or a tungsten stud. The overlapping region 72 of source contact 222 and of gate cap layer 58 of gate contact 220, as shown in FIG. 12, is typical of diffusion contacts known as borderless contacts.
Thus, as shown in FIGS. 11 and 12, an exemplary trench-sidewall array device 60 results from the exemplary process described above. As shown, n+ diffusion regions 18, 62 under diffusion contact 64 adjacent to trench 20 serve as the source and drain of device 60. A channel 66 results in substrate 24 (p-well 50) adjacent faceted sidewalls 32 of trench 20. Although device 60 as shown in FIG. 11 has been fabricated across the (011) plane, device 60 may also be fabricated across the (001) plane. The surface of substrate 24 is typically along the (100) plane. Thus, device 60 may be along a crystallographic plane in the same family as the substrate surface {001}, or may be on a different crystallographic plane (011) in a different family, as shown in FIG. 11.
As stated above, the crystal dependency of standard oxidation processes used for forming, for example, the gate oxide and LOCOS collar in DRAM trenches manufactured by the traditional process described above, as well as in other processes known in the art, often results in a differential thickness in the oxide walls. The differential oxide wall thickness causes undesired effects. Among those effects are potential dislocations.
The present invention provides a process, and a semiconductor memory device manufactured by that process, for reducing the undesired effects of orientation-dependent oxidation and avoiding such potential dislocations. It should be noted that the conventional process described above resulting in the above structure is merely one exemplary process for creating a DRAM cell having a vertical transistor. Other processes known in the art can similarly benefit from the improvements of the present invention.
The present invention provides a process for forming an oxide layer on a sidewall of a trench in a substrate. The process comprises the steps of forming the trench in the substrate; forming a nitride interface layer over a portion of the trench sidewall; forming an amorphous layer over the nitride interface layer; and oxidizing the amorphous layer to form the oxide layer.
The oxidation step is preferably of sufficient duration to completely consume the amorphous layer over the nitride interface layer. The oxidation step may further be of sufficient duration, however, to oxidize a portion of the trench sidewall under the nitride interface layer. Typically, the amorphous layer is formed having a thickness that is approximately half of a desired oxide layer thickness. For example, the amorphous layer may have a thickness of about 25 to about 50 Angstroms when the oxide layer grows to a thickness of about 50 to about 100 Angstroms.
The process may be used, for example, to form a gate oxide for a vertical transistor, or an isolation collar. Where the process is used to form an isolation collar, the process further comprises forming a nitride-oxynitride barrier layer over the amorphous silicon layer, and then etching away a portion of the nitride-oxynitride barrier layer to define the portion of the amorphous silicon to be oxidized.
The invention also comprises a semiconductor memory device having a substrate and a trench in the substrate with a sidewall. An isolation collar comprising an isolation collar oxide layer is located on the trench sidewall in an upper portion of the trench. A vertical gate oxide comprising a gate oxide layer is located on the trench sidewall in the upper portion of the trench above the isolation collar. The isolation collar oxide layer may be disposed over an isolation collar nitride interface layer between the isolation collar oxide layer and the trench sidewall, the gate oxide layer may be disposed over a gate nitride interface layer between the gate oxide layer and the trench sidewall, or both.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention